The present invention relates to dynamic random access memory (DRAM) cells and methods of fabricating them. More particularly, the invention relates to single polysilicon layer planar DRAM cells having high capacitance.
Many processes exist for forming DRAM cells, either in dedicated DRAM memory chips or as embedded DRAM regions in logic chips. Similarly, DRAM cells take many shapes and forms. The simplest employ a single access transistor, but other designs employ additional transistors as well. The storage capacitors in DRAM cells have taken many forms. For example, some are formed coplanar with the substrate surface, others as a trench extending into the substrate, still others as a fin protruding above the substrate surface, etc. The exotic trench and fin structures provide high surface area capacitor plates and therefore high capacitance cells. This allows a high density of DRAM cells to be provided on a single chip or chip region. Unfortunately, the processes for making such exotic structures are highly complex and can be quite difficult and expensive to implement.
DRAMs having planar capacitor plates are inherently easier to fabricate. However, because their planar capacitor plates have a relatively large storage surface for charge storage area per unit of chip surface area (in comparison to trench or fin designs, for example), competitive high density DRAM arrays may press the lower limits of cell capacitance. Unfortunately, it is not possible to reduce cell capacitance to very low levels. In current DRAM technology, the lower limit of cell capacitance is about 25 femtofarads. The capacitance of a cell is directly proportional to the dielectric layer's charge storage area and its dielectric constant. The cell capacitance is inversely proportional to the dielectric layer's thickness. Thus, because a planar-type DRAM capacitor has a relatively low charge storage surface area, it must have a dielectric layer that is relatively thin and/or has a relatively high dielectric constant (in comparison to fin and trench type capacitors) in order to be competitive.
Most conventional processes of forming planar DRAM cells involve using two dielectrics: one as the capacitor dielectric (typically an oxynitride) and one as the access transistor dielectric (typically oxide). A few simpler processes employ a single dielectric layer as both the gate dielectric and the capacitor dielectric. Typically, the material used in single dielectric processes is silicon oxide which has a dielectric constant of about 3.9. In current sub-micron processes, the gate oxide is typically grown to a thickness of less than about 50-100 angstroms. Under these constraints, planar DRAM cells must occupy more surface area than is suitable for many applications. Further, most all processes of forming DRAMs employ two polysilicon layers, adding significant complexity to the process.
What is needed therefore is an improved process in which a planar DRAM cell design can be implemented with reduced substrate surface area being occupied.